This invention relates to the field of telecommunications, and more particularly to clock synchronization and fault protection for a telecommunications device.
Many telecommunications devices include backplanes for transmitting digital information between components of the devices. For example, a telecommunications switching system might include a backplane for transmitting digital data representing voice signals between cards associated with incoming and outgoing ports. Typically, such a system would also include a mechanism to allow the system to detect a timing error, loss of clock synchronization, or other clock failure associated with the total or partial failure of one of the cards or of its clock generation functionality. Successful operation of the system in many instances will depend heavily upon the ability of this mechanism to detect and respond appropriately to such a failure to meet often stringent availability, flexibility, and other requirements placed on the system.
As the telecommunications industry continues to dominate the growth of the global economy, meeting availability, flexibility, and other requirements placed on switching and other systems has become increasingly important. High availability is generally considered as exceeding 99.999 percent availability, amounting to less than approximately five minutes of xe2x80x9cdown timexe2x80x9d each year, and generally requires a system to be able to detect and to autonomously handle certain faults, such as a clock failure associated with a card or its clock generation functionality, without immediate human intervention. Providing high availability is often a de facto if not explicit competitive requirement for many telecommunications manufacturers.
However, prior techniques for detecting and responding to clock failures are often inadequate to meet high availability and other requirements. One such technique involves monitoring a reference clock signal and, in response to a loss of the reference clock signal, initiating a delayed or even a xe2x80x9chardxe2x80x9d switchover to a redundant reference clock signal. Hard switchovers of this type often require significant time to accomplish and may result in xe2x80x9cslipsxe2x80x9d in the network, lost calls, and other losses of data integrity. Even a delayed switchover may be of little use if the secondary reference clock signal has also been lost or is otherwise unsuitable. Prior techniques often do not allow the system to continue operating, uninterrupted and maintaining substantial data integrity, despite such clock failures. Moreover, although a system using such a technique might raise an alarm to indicate the clock failure, before or after initiating the switchover, the system might not be able to determine the source of the errorxe2x80x94either the source of the reference clock signal or the card itselfxe2x80x94which may lead to unnecessary switchovers and other undesirable consequences. These and other deficiencies are particularly apparent in high availability backplane environments of telecommunications devices.
According to the present invention, disadvantages and problems associated with clock synchronization and fault protection in telecommunications devices have been substantially reduced or eliminated.
In one embodiment, a telecommunications device includes a synchronization bus and a controller coupled to the bus that generates a system clock signal according to a primary reference clock signal and communicates the system clock signal using the bus. The controller detects a loss of the primary reference clock signal and, in response, continues generating the system clock signal, determines acceptability of a secondary reference clock signal, switches from the primary reference clock signal to the secondary reference clock signal if the secondary reference clock signal is acceptable, and in response to the switch generates the system clock signal according to the secondary reference clock signal.
In another embodiment, a controller for operation in a telecommunications device is coupled to a synchronization bus of the device. The controller generates a system clock signal according to a primary reference clock signal and communicates the system clock signal using the bus. The controller detects a loss of the primary reference clock signal and, in response, continues generating the system clock signal, determines acceptability of a secondary reference clock signal, switches from the primary reference clock signal to the secondary reference clock signal if the secondary reference clock signal is acceptable, and in response to the switch generates the system clock signal according to the secondary reference clock signal.
The present invention may provide a number of important technical advantages over prior techniques for detecting and responding to a timing error, loss of synchronization, or other clock failures, particularly within a high availability backplane environment. The present invention provides multiple layers of fault protection, including detecting a clock failure, readily identifying its source, and responding to the failure to minimize its impact on the system. In one embodiment, these operations are accomplished quickly and autonomously. Also unlike some prior techniques, the present invention does not require a hard switchover to a redundant reference clock signal, reducing the likelihood of slips in the network, lost calls, or other undesirable losses of data integrity. Nor does the present invention require that a single secondary reference signal be available and acceptable to avoid such losses of data integrity. The present invention helps prevent single points of failure from propagating within the system, thereby helping to reduce down time and to satisfy high availability and other requirements. As a result of these and other important technical advantages, the present invention is particularly suited for incorporation in a variety of switching and other modern telecommunications devices having high availability backplane environments.